CMOS imager and method of formation

ABSTRACT

A CMOS imager having an epitaxial layer formed below pixel sensor cells is disclosed. An epitaxial layer is formed between a semiconductor substrate and a photosensitive region to improve the cross-talk between pixel cells. The thickness of the epitaxial layer is optimized so that the collection of signal carriers by the photosensitive region is maximized.

FIELD OF THE INVENTION

[0001] The present invention relates to improved semiconductor imagingdevices and, in particular, to CMOS imagers with improved colorseparation and sensitivity.

BACKGROUND OF THE INVENTION

[0002] The semiconductor industry currently uses different types ofsemiconductor-based imagers, such as charge coupled devices (CCDs),photodiode arrays, charge injection devices and hybrid focal planearrays, among others.

[0003] CCD technology is often used for image acquisition and has anumber of advantages which makes it the preferred technology,particularly for small size imaging applications. CCDs are capable oflarge formats with small pixel size and they employ low noise chargedomain processing techniques. CCD imagers suffer, however, from a numberof disadvantages. For example, they are susceptible to radiation damage,they exhibit destructive read-out over time, they require good lightshielding to avoid image smear and they have a high power dissipationfor large arrays. In addition, while offering high performance, CCDarrays are difficult to integrate with CMOS processing in part due to adifferent processing technology and to their high capacitances,complicating the integration of on-chip drive and signal processingelectronics with the CCD array. Further, CCDs may suffer from incompletecharge transfer from pixel to pixel which results in image smear.

[0004] Because of the inherent limitations in CCD technology, CMOSimagers have been increasingly used as low cost imaging devices. A fillycompatible CMOS sensor technology enabling a higher level of integrationof an image array with associated processing circuits would bebeneficial to many digital applications such as, for example, incameras, scanners, machine vision systems, vehicle navigation systems,video telephones, computer input devices, surveillance systems, autofocus systems, star trackers, motion detection systems, imagestabilization systems and data compression systems for high-definitiontelevision.

[0005] CMOS imagers have several advantages over CCD imagers, such as,for example, low voltage operation and low power consumption,compatibility with integrated on-chip electronics (control logic andtiming, image processing, and signal conditioning such as A/Dconversion), random access to the image data, and lower fabricationcosts. Additionally, low power consumption is achieved for CMOS imagersbecause only one row of pixels at a time needs to be active during thereadout and there is no charge transfer (and associated switching) frompixel to pixel during image acquisition. On-chip integration ofelectronics is particularly advantageous because of the potential toperform many signal conditioning functions in the digital domain (versusanalog signal processing) as well as to achieve a reduction in systemsize and cost.

[0006] A CMOS imager circuit includes a focal plane array of pixelcells, each one of the cells including either a photogate,photoconductor or a photodiode overlying a doped region of a substratefor accumulating photo-generated charge in the underlying portion of thesubstrate. A readout circuit is connected to each pixel cell andincludes at least an output field effect transistor formed in thesubstrate and a charge transfer section formed on the substrate adjacentthe photogate, photoconductor or photodiode having a sensing node,typically a floating diffusion node, connected to the gate of an outputtransistor. The imager may include at least one electronic device suchas a transistor for transferring charge from the charge accumulationregion of the substrate to the floating diffusion node and one device,also typically a transistor, for resetting the node to a predeterminedcharge level prior to charge transference.

[0007] In a CMOS imager, the active elements of a pixel cell perform thenecessary functions of: (1) photon to charge conversion; (2)accumulation of image charge; (3) transfer of charge to the floatingdiffusion node accompanied by charge amplification; (4) resetting thefloating diffusion node to a known state before the transfer of chargeto it; (5) selection of a pixel for readout; and (6) output andamplification of a signal representing pixel charge. Photo charge may beamplified when it moves from the initial charge accumulation region tothe floating diffusion node. The charge at the floating diffusion nodeis typically converted to a pixel output voltage by a source followeroutput transistor. The photosensitive element of a CMOS imager pixel istypically either a depleted p-n junction photodiode or a field induceddepletion region beneath a photogate. For photodiodes, image lag can beeliminated by completely depleting the photodiode upon readout.

[0008] A schematic view of an exemplary CMOS imaging circuit isillustrated in FIG. 1. As it will be described below, the CMOS imagingcircuit includes a photogate for accumulating photo-generated charge inan underlying portion of the substrate. It should be understood,however, that the CMOS imager may include a photodiode or other image tocharge converting device, in lieu of a photogate, as the initialaccumulator for photo-generated charge.

[0009]FIG. 1 shows a simplified photodetector circuit for a pixel cell14 of an exemplary CMOS imager using a photogate and a readout circuit60. It should be understood that while FIG. 1 shows the circuitry foroperation of a single pixel, in practical use there will be an M x Narray of pixels arranged in rows and columns with the pixels of thearray accessed using row and column select circuitry, as described inmore detail below.

[0010] The pixel cell 14 is shown in part as a cross-sectional view of asemiconductor substrate 16, which is typically a p-type silicon, havinga surface well of p-type material 20. An optional layer 18 of p-typematerial may be used, if desired. Substrate 16 may be formed of Si,SiGe, Ge, or GaAs, among others. Typically, the entire semiconductorsubstrate 16 is a p-type doped silicon substrate including a surfacep-well 20 (with layer 18 omitted), but many other options are possible,such as, for example p on p− substrates, p on p+ substrates, p-wells inn-type substrates or the like.

[0011] An insulating layer 22 of silicon dioxide, for example, is formedon the upper surface of p-well 20. The p-type layer may be a p-wellformed in substrate 16. A photogate 24, thin enough to pass radiantenergy or of a material which passes radiant energy, is formed on theinsulating layer 22. The photogate 24 receives an applied control signalPG which causes the initial accumulation of pixel charges in n+ region26. An n+ type region 26, adjacent to one side of the photogate 24, isformed in the upper surface of p-well 20. A transfer gate 28 is formedon insulating layer 22 between the n+type region 26 and a second n+ typeregion 30 formed in p-well 20. The n+ regions 26 and 30 and transfergate 28 form a charge transfer transistor 29 which is controlled by atransfer signal TX. The n+ region 30 is typically called a floatingdiffusion region. The n+ region 30 is also a node for passing chargeaccumulated thereat to the gate of a source follower transistor 36described below.

[0012] A reset gate 32 is also formed on insulating layer 22 adjacentand between the n+ type region 30 and another n+ region 34 which is alsoformed in p-well 20. The reset gate 32 and n+ regions 30 and 34 form areset transistor 31 which is controlled by a reset signal RST. The n+type region 34 is coupled to voltage source V_(DD), of for example, 5volts. The transfer and reset transistors 29, 31 are n-channeltransistors as described in this implementation of a CMOS imager circuitin a p-well. As known in the art, it is also possible to implement aCMOS imager in an n-well, in which case each of the transistors would bep-channel transistors. It should also be noted that, while FIG. 1 showsthe use of a transfer gate 28 and associated transistor 29, thisstructure provides advantages, but is not required.

[0013] Pixel cell 14 also includes two additional n-channel transistors,a source follower transistor 36 and a row select transistor 38.Transistors 36, 38 are coupled in series, source to drain, with thesource of transistor 36 also coupled over lead 40 to voltage sourceV_(DD) and the drain of transistor 38 coupled to a lead 42. The drain ofthe row select transistor 38 is connected via conductor 42 to the drainsof similar row select transistors for other pixels in a given pixel row.A load transistor 39 is also coupled between the drain of transistor 38and a voltage source V_(SS), of for example 0 volts. Transistor 39 iskept on by a signal V_(LN) applied to its gate.

[0014] The imager includes a readout circuit 60 (FIG. 1) which includesa signal sample and hold (S/H) circuit including a S/H n-channel fieldeffect transistor 62 and a signal storage capacitor 64 connected to thesource follower transistor 36 through row transistor 38. The other sideof the capacitor 64 is connected to a source voltage V_(SS). The upperside of the capacitor 64 is also connected to the gate of a p-channeloutput transistor 66. The drain of the output transistor 66 is connectedthrough a column select transistor 68 to a signal sample output nodeV_(OUTS) and through a load transistor 70 to the voltage supply V_(DD).A signal called “signal sample and hold” (SHS) briefly turns on the S/Htransistor 62 after the charge accumulated beneath the photogateelectrode 24 has been transferred to the floating diffusion node 30 andfrom there to the source follower transistor 36 and through row selecttransistor 38 to line 42, so that the capacitor 64 stores a voltagerepresenting the amount of charge previously accumulated beneath thephotogate electrode 24.

[0015] The readout circuit 60 also includes a reset sample and hold(S/H) circuit including a S/H transistor 72 and a signal storagecapacitor 74 connected through the S/H transistor 72 and through the rowselect transistor 38 to the source of the source follower transistor 36.The other side of the capacitor 74 is connected to the source voltageV_(SS). The upper side of the capacitor 74 is also connected to the gateof a p-channel output transistor 76. The drain of the output transistor76 is connected through a p-channel column select transistor 78 to areset sample output node V_(OUTR) and through a load transistor 80 tothe supply voltage V_(DD). A signal called “reset sample and hold” (SHR)briefly turns on the S/H transistor 72 immediately after the resetsignal RST has caused reset transistor 31 to turn on and reset thepotential of the floating diffusion node 30, so that the capacitor 74stores the voltage to which the floating diffusion node 30 has beenreset.

[0016] The readout circuit 60 provides correlated sampling of thepotential of the floating diffusion node 30, first of the reset chargeapplied to node 30 by the reset transistor 31 and then of the storedcharge from the photogate 24. The two samplings of the diffusion node 30charges produce respective output voltages V_(OUTR) and V_(OUTS) of thereadout circuit 60. These voltages are then subtracted(V_(OUTS)−V_(OUTR)) by subtractor 82 to provide an output signalterminal 81 which is an image signal independent of pixel to pixelvariations caused by fabrication variations in the reset voltagetransistor 31 which might cause pixel to pixel variations in the outputsignal.

[0017]FIG. 2 illustrates a block diagram for a CMOS imager having apixel array 200 with each pixel cell being constructed in a mannersimilar to that of pixel cell 14 of FIG. 1. Pixel array 200 comprises aplurality of pixels arranged in a predetermined number of columns androws. The pixels of each row in array 200 are all turned on at the sametime by a row select line, such as line 86, and the pixels of eachcolumn are selectively output by a column select line, such as line 42.A plurality of rows and column lines are provided for the entire array200. The row lines are selectively activated by the row driver 210 inresponse to row address decoder 220 and the column select lines areselectively activated by the column driver 260 in response to columnaddress decoder 270. Thus, a row and column address is provided for eachpixel. The CMOS imager is operated by the control circuit 250 whichcontrols address decoders 220, 270 for selecting the appropriate row andcolumn lines for pixel readout, and row and column driver circuitry 210,260 which apply driving voltage to the drive transistors of the selectedrow and column lines.

[0018]FIG. 3 shows a simplified timing diagram for the signals used totransfer charge out of pixel cell 14 of the CMOS imager of FIG. 1. Thephotogate signal PG is nominally set to 5V and pulsed from 5V to 0Vduring integration. The reset signal RST is nominally set at 2.5V. Asillustrated in FIG. 3, the process begins at time t₀ by briefly pulsingreset voltage RST to 5V. The RST voltage, which is applied to the gate32 of the reset transistor 31, causes transistor 31 to turn on and thefloating diffusion node 30 to charge to the V_(DD) voltage present at n+region 34 (less the voltage drop V_(TH) of transistor 31). This resetsthe floating diffusion node 30 to a predetermined voltage(V_(DD)−V_(TH)). The charge on the floating diffision node 30 is appliedto the gate of the source follower transistor 36 to control the currentpassing through transistor 38, which has been turned on by a row select(ROW) signal, and load transistor 39. This current is translated into avoltage on line 42 which is next sampled by providing a SHR signal tothe S/H transistor 72, which charges capacitor 74 with the sourcefollower transistor output voltage on line 42 representing the resetcharge present at floating diffision node 30. The PG signal is nextpulsed to 0 volts, causing charge to be collected in n+ region 26.

[0019] A transfer gate voltage TX, similar to the reset pulse RST, isthen applied to transfer gate 28 of transistor 29 to cause the charge inn+ region 26 to transfer to floating diffision node 30. It should beunderstood that, for the case of a photogate, the transfer gate voltageTX may be pulsed or held to a fixed DC potential. For the implementationof a photodiode with a transfer gate, the transfer gate voltage TX mustbe pulsed. The new output voltage on line 42 generated by sourcefollower transistor 36 current is then sampled onto capacitor 64 byenabling the sample and hold switch 62 by signal SHS. The column selectsignal is next applied to transistors 68 and 70 and the respectivecharges stored in capacitors 64 and 74 are subtracted in subtractor 82to provide a pixel output signal at terminal 81. It should also be notedthat CMOS imagers may dispense with the transfer gate 28 and associatedtransistor 29, or retain these structures while biasing the transfertransistor 29 to an always “on” state.

[0020]FIG. 4 shows a 2×2 portion of pixel array 200 illustratedschematically in FIG. 2. Pixel array 200 comprises a plurality of pixelsarranged in a predetermined number of columns and rows. The pixels ofeach row in array 200 are all turned on at the same time by a row selectline, for example, line 86, and the pixels of each column areselectively output by a column select line, e.g., line 42. A pluralityof rows and column lines are provided for the entire array 200. The rowlines are selectively activated by the row driver 210 in response to rowaddress decoder 220 and the column select lines are selectivelyactivated by the column driver 260 in response to column address decoder270. Thus, a row and column address is provided for each pixel. The CMOSimager is operated by the control circuit 250 which controls addressdecoders 220, 270 for selecting the appropriate row and column lines forpixel readout, and row and column driver circuitry 210, 260 which applydriving voltage to the drive transistors of the selected row and columnlines.

[0021] Quantum efficiency is a problem in some imager applications dueto the diffusion of signal carriers out of the photosite and into thesubstrate, where they become effectively lost. The loss of signalcarriers results in decreased signal strength, increased cross-talk, andthe reading of an improper value for the adjacent pixels.

[0022] There is needed, therefore, an improved pixel sensor cell for usein an imager that exhibits improved color separation, improved quantumefficiency, a better signal-to-noise ratio, and reduced cross-talk. Amethod of fabricating a pixel sensor cell exhibiting these improvementsis also needed.

SUMMARY OF THE INVENTION

[0023] The present invention provides a method for improving the crosstalk between pixel sensor cells of CMOS imagers. According to thepresent invention, optical cross-talk between pixel cells is improved byproviding an epitaxial layer between the semiconductor substrate and thephotosensitive region. The epitaxial layer induces an electric fieldwhich reflects signal carriers back to the photosensitive region. Thethickness of the epitaxial layer may be optimized so that the collectionof signal carriers by the photosensitive region and the photoresponsefor different wavelengths are maximized.

[0024] Additional advantages and features of the present invention willbe apparent from the following detailed description and drawings whichillustrate preferred embodiments of the invention.

BRIEF DESCRIPTION OF THE DRAWINGS

[0025]FIG. 1 is a representative circuit of a active pixel cell of aCMOS imaging system.

[0026]FIG. 2 is a block diagram of a CMOS pixel sensor chip.

[0027]FIG. 3 is a representative timing diagram of a CMOS imager.

[0028]FIG. 4 is a cross-sectional and schematic view of a color pixel.

[0029]FIG. 5 is a cross-sectional and schematic view of a pixel cellfabricated in accordance with an embodiment of the present invention.

[0030]FIG. 6 is a cross-sectional view of the pixel cell of FIG. 4 at astage of processing subsequent to that shown in FIG. 5.

[0031]FIG. 7 is a cross-sectional view of the pixel cell of FIG. 4 at astage of processing subsequent to that shown in FIG. 6.

[0032]FIG. 8 is a cross-sectional view of the pixel cell of FIG. 4 at astage of processing subsequent to that shown in FIG. 7.

[0033]FIG. 9 is an illustration of a computer system having a CMOSimager with pixel cells formed according to the present invention.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

[0034] In the following detailed description, reference is made to theaccompanying drawings which form a part hereof, and in which is shown byway of illustration specific embodiments in which the invention may bepracticed. These embodiments are described in sufficient detail toenable those skilled in the art to practice the invention, and it is tobe understood that other embodiments may be utilized, and thatstructural, logical and electrical changes may be made without departingfrom the spirit and scope of the present invention.

[0035] The terms “wafer” and “substrate” are to be understood as asemiconductor-based material including silicon-on-insulator (SOI) orsilicon-on-sapphire (SOS) technology, doped and undoped semiconductors,epitaxial layers of silicon supported by a base semiconductorfoundation, and other semiconductor structures. Furthermore, whenreference is made to a “wafer” or “substrate” in the followingdescription, previous process steps may have been utilized to formregions or junctions in the base semiconductor structure or foundation.In addition, the semiconductor need not be silicon-based, but could bebased on silicon-germanium, germanium, or gallium arsenide.

[0036] The term “pixel” refers to a picture element unit cell containinga photosensor and transistors for converting electromagnetic radiationto an electrical signal. For purposes of illustration, a representativepixel is illustrated in the figures and description herein and,typically, fabrication of all pixels in an imager will proceedsimultaneously in a similar fashion.

[0037] The term “well” refers to a doped region in a substrate where thepeak concentration of the dopant is lower than that of the electricallyactive region of any device which may be eventually formed in the well.

[0038] Referring now to the drawings, where like elements are designatedby like reference numerals, FIGS. 5-8 illustrate an exemplary embodimentof a method of forming pixel cells 100 (FIG. 8) in a well formed in anepitaxial layer 160. FIG. 5 illustrates a substrate 16, which may be anyof the types of substrates described above. Although reference to thesubstrate 16 will be made in this application as to a p-type siliconsubstrate 16, it must be understood that many other options arepossible, for example, p on p− substrates, or p on p+ substrates, SOIsubstartes, or the like. Further, the invention has equal application toother semiconductor substrates, for example, silicon-germanium,germanium, silicon-on-saphire, or gallium-arsenide substrates, amongmany others.

[0039] Next, as illustrated in FIG. 6, an epitaxial layer 160 is formedover the p-type silicon substrate 16. The epitaxial layer 160 is of afirst conductivity type, which for exemplary purposes is treated asp-type. Thus, in an exemplary embodiment of the invention, the epitaxiallayer 160 is a p-type epitaxial layer 160 formed by a process such asliquid phase epitaxy (LPE), ultra high vacuum (UHV) chemical vapordeposition (CVD), vapor phase epitaxy (VPE), or metal organic vaporphase epitaxy (MOVPE), among others.

[0040] In an exemplary embodiment of the invention, the p-type epitaxiallayer 160 (FIG. 6) is a p-type epitaxial silicon layer 160 which isgrown by epitaxy in a reaction chamber at high temperatures, of about900-1200° C., and by employing a silicon gas source that introduces agaseous species containing silicon (Si) into the reaction chamber. Asknown in the art, the silicon gas source may be silane (SiH₄), higherorder silanes, such as disilane (Si₂H₆), as well as other gaseoussources of silicon, such as dichlorsilane (SiH₂Cl₂), trichlorsilane(SiHCl₃), or tetrachlorsilane (SiCl₄). The p-type epitaxial siliconlayer 160 (FIG. 6) is grown over the p-type silicon substrate 16 to athickness of about 10,000 Angstroms to about 150,000 Angstroms, morepreferably of about 30,000 Angstroms to about 100,000 Angstroms, andmost preferably of about 60,000 Angstroms.

[0041] Although the above-mentioned thickness ranges are preferred, theinvention is not limited to these values. In fact, and as it will beexplained in more detail below, an important aspect of the invention isthat the thickness of the p-type epitaxial silicon layer 160 may betailored according to the device characteristics to control how signalcarriers, for example photogenerated electrons, are collected in thephotosensitive region of the CMOS imager. As explained in more detailbelow, by optimizing the thickness of the p-type epitaxial silicon layer160, the collection of the signal carriers is maximized and thecross-talk between pixel cells is accordingly minimized.

[0042] Referring now to FIG. 7 and in accordance with an exemplaryembodiment of the invention, a well 20 is formed in the p-type epitaxialsilicon layer 160 and over the entire wafer by suitable means, forexample blanket ion implantation. The layer or well 20 is of a firstconductivity type, which, as mentioned above, is treated as p-type.Although the invention will be described with reference to the p-typeepitaxial silicon layer 160 having well 20 formed therein, the inventionis not limited to this exemplary embodiment, and it also contemplatesthe formation of the p-type epitaxial silicon layer 160 without a wellformed therein. In addition, although the present invention will bedescribed with the p-type well 20 formed after the formation of thep-type epitaxial silicon layer 160 and before the formation of theisolation regions, the p-type well 20 may be also implanted at a laterstage of the process, for example after field oxide formation. Theimplant may be patterned so that the pixel array well and the peripherylogic well, which contains logic circuits for transferring charge fromthe pixel array, could have different conductivities and/or dopingprofiles.

[0043] Ion implantation is performed by placing the p-type siliconsubstrate 16 in an ion implanter, and implanting appropriate dopant ionsinto the p-type epitaxial silicon layer 160 at an energy of 10 keV to 5MeV to form p-type wells 20. In an exemplary embodiment of the presentinvention, the p-type well 20 is a retrograde p-type well having adopant concentration that is lowest at the surface, and highest at thebottom of the well. According to this embodiment, the dopantconcentration at the top of the p-type retrograde well 20 is within therange of about 5×10¹⁴ to about 1×10¹⁸ atoms per cm³, and is preferablywithin the range of about 1×10¹⁶ to about 1×10¹⁷ atoms per cm³, and mostpreferably is about 4×10¹⁶ atoms per cm³. At the bottom of the p-typewell 20, the dopant concentration is within the range of about 1×10¹⁶ toabout 2×10¹⁸ atoms per cm³, and is preferably within the range of about2×10¹⁶ to about 1×10¹⁸ atoms per cm³, and most preferably is about1×10¹⁷ atoms per cm³. If the retrograde well 20 is to be a p-type well,a p-type dopant, such as boron, or indium is implanted, and if theretrograde well 20 is to be an n-type well, an n-type dopant, such asarsenic, antimony, or phosphorous is implanted. The resultant structureis shown in FIG. 7. Multiple high energy implants may be used to tailorthe dopant profile of the p-type well 20.

[0044] Also illustrated in FIG. 7 are field oxide regions 114 which maybe formed around later formed pixel cells 100, and according to anembodiment of the invention, after the formation of the p-type well 20.The field oxide regions are formed by any known technique such asthermal oxidation of the underlying silicon in a LOCOS process or byetching trenches and filling them with oxide in an STI process.Following field oxide 114 formation, if the p-type well 20 has not yetbeen formed, it may then be formed by blanket implantation or by maskedimplantation to produce the well 20 shown in FIG. 7.

[0045] Subsequent to formation of the p-type well 20 and of the fieldoxide regions 114, the devices of the pixel sensor cell 100 (FIG. 8),including the photogate 24, the transfer gate 28, reset transistor 31,the source follower 36 and the row select transistor 38 are formed bywell-known methods, all being depicted in FIG. 8. Doped regions 26,30,and 34 are formed in the p-type well 20, and are doped to a secondconductivity type, which for exemplary purposes will be considered to ben-type. The doping level of the doped regions 26, 30, 34 may vary butshould be higher than the doping level at the top of the p-type well 20,and greater than 5×10¹⁶ atoms per cm³. If desired, multiple masks andresists may be used to dope these regions to different levels. Dopedregion 26 may be variably doped, such as either n+ or n− for an n−channel device. Doped region 34 should be strongly doped, i.e., for ann-channel device, the doped region 34 will be doped as n+. Doped region30 is typically strongly doped (n+), and would not be lightly doped (n−)unless a buried contact is also used.

[0046] The single p-type epitaxial silicon layer 160 with the p-typewell 20 formed therein spans all pixels in the array of pixels, asdepicted in FIG. 8. A second epitaxial layer with a second n- or p-typewell (not shown) may be formed in the substrate 16, and may contain theperipheral circuitry such as, for example, logic circuitry formedtherein. This second well may be doped similarly or differently from thefirst retrograde well 20.

[0047] The transistor gates forming the pixel cell 100 are a photogate24, a transfer gate 28 for transfer transistor 29, and a resettransistor gate 32 for the reset transistor 31. In addition, thephotosensitive element in the pixel cell 100 is shown to be a photogate24, but other photosensitive elements such as a photodiode or aphotoconductor could be used. The transfer gate 28 and the reset gate 32include a gate oxide layer 106 on the p-type well 20, and a conductivelayer 108 of doped polysilicon, tungsten, or other suitable materialover the gate oxide layer 106. An insulating cap layer 110 of, forexample, silicon dioxide, silicon nitride, or ONO (oxide-nitride-oxide),may be formed if desired; also a more conductive layer such as asilicide layer (not shown) may be used between the conductive layer 108and the cap 110 of the transfer gate stack 28, source follower gate, rowselect gate, and reset gate stack 32, if desired. Insulating sidewalls112 are also formed on the sides of the gate stacks 28, 32. Thesesidewalls may be formed of, for example, silicon dioxide or siliconnitride or ONO. The transfer gate 28 and/or transfer transistor 29 arenot required but may advantageously be included. If they are omitted,doped region 26 connects with doped region 30. The photogate 24 is asemitransparent conductor and is shown as an overlapping gate. In thiscase there is a second gate oxide 105 over the well and under thephotogate.

[0048] Underlying the photogate 24 is the doped region 26 called thephotosite, where photogenerated charges are stored. In between the resettransistor gate 32 and the transfer gate 28 is a doped region 30 that isthe source for the reset transistor 31, and on the other side of thereset transistor gate 32 is a doped region 34 that acts as a drain forthe reset transistor 31. The doped regions 26, 30, 34 are doped to asecond conductivity type, which for exemplary purposes is treated asn-type. The second doped region 30 is the floating diffusion region,sometimes also referred to as a floating diffusion node. The third dopedregion 34 is connected to voltage source Vdd.

[0049] As shown in FIG. 8, as light radiation 12 in the form of photonsstrikes the photosite 26, photo-energy is converted to electricalsignals, for example, carriers 120, which are stored in the photosite26. The absorption of light creates electron-hole pairs. For the case ofan n-doped photosite in a p-well, it is the electrons that are stored.For the case of a p-doped photosite in an n-well, it is the holes thatare stored. In the exemplary pixel cell 100 of FIG. 8 having n-channeldevices formed in the p-type epitaxial layer 160, the carriers 120stored in the photosite 26 are electrons.

[0050] The p-type epitaxial layer 160 acts to reduce carrier loss to thesubstrate 16 by forming a concentration gradient that modifies the banddiagram and serves to reflect electrons back towards the photosite 26,thereby increasing quantum efficiency of the pixel 100. The formation ofthe p-type epitaxial layer 160 increases the dopant concentration atinterface 161 (FIG. 8), defined as the interface between the p-typeepitaxial layer 160 and the p-type silicon substrate 16. The increase ofp-type dopant concentration at the interface 161 further results in anelectric field E (FIG. 8) directed away from the surface of the pixelsensor cell 100 and which acts as a reflective barrier for the electronsor carriers 120 in substrate 16. Thus, if the p-type epitaxial layer 160is chosen to have a thickness of about 80,000 Angstroms, red light,which is typically absorbed deep in the silicon substrate, will beabsorbed at about the epitaxial layer 160/silicon substrate 16 interface161. Because the increased doping concentration at this interfacecreates a strong electric field, the red photogenerated electrons arereflected back towards the surface of the p-type silicon substrate 16and the photosite 26.

[0051] Similarly, if the p-type epitaxial layer 160 is chosen to have athickness of about 10,000 Angstroms, blue light, which is typicallyabsorbed close to the surface of the silicon surface, will be absorbedat the epitaxial layer 160/silicon substrate 16 interface 161 and, thus,close to the surface of the p-type silicon substrate 16. Again, theincreased doping concentration at the interface 161 creates an electricfield which reflects back blue photogenerated electrons towards thesurface of the p-type silicon substrate 16 and the photosite 26. Thisway, by adjusting the thickness of the p-type epitaxial layer 160 forrespective color pixel cells, the photogenerated electrons correspondingto a particular color wavelength are reflected back to the photosite 26,the collection of such photogenerated electrons is maximized and,accordingly, the cross-talk between pixel cells is minimized.

[0052] The pixel sensor cell 100 is essentially complete at this stage,and conventional processing methods may be used to form contacts andwiring to connect gate lines and other connections in the pixel cell100. For example, the entire surface may then be covered with apassivation layer of, for example, silicon dioxide, BSG, PSG, or BPSG,which is CMP planarized and etched to provide contact holes, which arethen metallized to provide contacts to the photogate, reset gate, andtransfer gate. Conventional multiple layers of conductors and insulatorsmay also be used to interconnect the structures in the manner shown inFIG. 1.

[0053] A typical processor based system which includes a CMOS imagerdevice according to the present invention is illustrated generally at400 in FIG. 9. A processor based system is exemplary of a system havingdigital circuits which could include CMOS imager devices. Without beinglimiting, such a system could include a computer system, camera system,scanner, machine vision system, vehicle navigation system, videotelephone, surveillance system, auto focus system, star tracker system,motion detection system, image stabilization system and data compressionsystem for high-definition television, all of which can utilize thepresent invention.

[0054] A processor system, such as a computer system, for examplegenerally comprises a central processing unit (CPU) 444, for example, amicroprocessor, that communicates with an input/output (I/O) device 446over a bus 452. The CMOS imager 442 also communicates with the systemover bus 452. The computer system 400 also includes random access memory(RAM) 448, and, in the case of a computer system may include peripheraldevices such as a floppy disk drive 454 and a compact disk (CD) ROMdrive 456 which also communicate with CPU 444 over the bus 452. CMOSimager 442 is preferably constructed as an integrated circuit whichincludes pixels containing a photosensor, such as a photogate orphotodiode, formed in an epitaxial layer, as previously described withrespect to FIGS. 5-8. The CMOS imager 442 may be combined with aprocessor, such as a CPU, digital signal processor or microprocessor,with or without memory storage in a single integrated circuit, or may beon a different chip than the processor.

[0055] The present invention encompasses a pixel sensor cell formed inan epitaxial layer. The pixel sensor cell has improved quantumefficiency and an improved signal-to-noise ratio due to the presence ofa doping gradient induced electric field created in the bottom of theepitaxial layer which reflects signal carriers back to thephotosensitive node. By reflecting photogenerated carriers back to thestorage node, the epitaxial layer also reduces the number of carriersdiffusing to adjacent pixels and so also reduces cross-talk.

[0056] It should again be noted that although the invention has beendescribed with specific reference to CMOS imaging circuits having aphotogate and a floating diffusion region, the invention has broaderapplicability and may be used in any CMOS imaging apparatus. Similarly,the process described above is but one method of many that could beused. The above description and drawings illustrate preferredembodiments which achieve the objects, features and advantages of thepresent invention. It is not intended that the present invention belimited to the illustrated embodiments. Any modification of the presentinvention which comes within the spirit and scope of the followingclaims should be considered part of the present invention.

What is claimed as new and desired to be protected by Letters Patent ofthe United States is:
 1. A pixel sensor cell for an imaging device, saidpixel sensor cell comprising: an epitaxial layer of a first conductivitytype formed over a semiconductor substrate; a photosensitive chargecollection region formed in said epitaxial layer; and a doped region ofa second conductivity type formed in said epitaxial layer for receivingcharges transferred from said photosensitive charge collection region.2. The pixel sensor cell of claim 1, wherein the first conductivity typeis p-type, and the second conductivity type is n-type.
 3. The pixelsensor cell of claim 2, wherein said epitaxial layer is a p-typeepitaxial silicon layer.
 4. The pixel sensor cell of claim 3, whereinsaid p-type epitaxial silicon layer is a thermally grown p-typeepitaxial silicon layer.
 5. The pixel sensor cell of claim 1, whereinsaid epitaxial layer has a thickness of about 10,000 Angstroms to about150,000 Angstroms.
 6. The pixel sensor cell of claim 5, wherein saidepitaxial layer has a thickness of about 30,000 Angstroms to about100,000 Angstroms.
 7. The pixel sensor cell of claim 6, wherein saidepitaxial layer has a thickness of about 60,000 Angstroms.
 8. The pixelsensor cell of claim 1, wherein the first conductivity type is n-type,and the second conductivity type is p-type.
 9. The pixel sensor cell ofclaim 1 further comprising a well of a first conductivity type formed insaid epitaxial layer.
 10. The pixel sensor cell of claim 9, wherein saidwell is doped with a dopant selected from the group consisting ofarsenic, antimony, and phosphorous.
 11. The pixel sensor cell of claim9, wherein said well has a dopant concentration within the range ofabout 1×10¹⁶ to about 2×10¹⁸ atoms per cm³ at the bottom of said well.12. The pixel sensor cell of claim 11, wherein said well has a dopantconcentration within the range of about 5×10¹⁴ to about 1×10¹³ atoms percm³ at the top of said well.
 13. The pixel sensor cell of claim 9,wherein said well has a dopant concentration within the range of about2×10¹⁶ to about 1×10¹⁸ atoms per cm³ at the bottom of said well.
 14. Thepixel sensor cell of claim 13, wherein said well has a dopantconcentration within the range of about 1×10¹⁶ to about 1×10¹⁷ atoms percm³ at the top of said well.
 15. The pixel sensor cell of claim 1,further comprising a photosensor formed over said photosensitive chargecollection region for controlling the collection of charges in saidphotosensitive region.
 16. The pixel sensor cell of claim 15, whereinsaid photosensor is a photodiode sensor.
 17. The pixel sensor cell ofclaim 15, wherein said photosensor is a photogate sensor.
 18. The pixelsensor cell of clam 15, wherein said photosensor is a photoconductorsensor.
 19. The pixel sensor cell of claim 9, further comprising atransfer gate formed over said well between said photosensor and saiddoped region.
 20. The pixel sensor cell of claim 9, further comprising areset transistor formed in said well for periodically resetting a chargelevel of said doped region.
 21. The pixel sensor cell of claim 1,wherein said photosensitive charge collection region comprises a dopedregion of a second conductivity type.
 22. A pixel sensor cell for animaging device, said pixel sensor cell comprising: an epitaxial siliconlayer of a first conductivity type formed in a substrate; a retrogradewell of a first conductivity type formed in said epitaxial siliconlayer; a photosensor formed in said retrograde well; a reset transistorhaving a gate stack formed over said retrograde well; a floatingdiffusion region of a second conductivity type formed in said retrogradewell between said photosensor and reset transistor for receiving chargesfrom said photosensor, said reset transistor operating to periodicallyreset a charge level of said floating diffusion region; and an outputtransistor having a gate electrically connected to said floatingdiffusion region.
 23. The pixel sensor cell of claim 22, wherein saidepitaxial silicon layer has a thickness of about 10,000 Angstroms toabout 150,000 Angstroms.
 24. The pixel sensor cell of claim 23, whereinsaid epitaxial silicon layer has a thickness of about 30,000 Angstromsto about 100,000 Angstroms.
 25. The pixel sensor cell of claim 24,wherein said epitaxial silicon layer has a thickness of about 60,000Angstroms.
 26. The pixel sensor cell of claim 22, wherein said epitaxialsilicon layer is a thermally grown epitaxial silicon layer.
 27. Thepixel sensor cell of claim 22, wherein said photosensor furthercomprises a doped region of a second conductivity type located in saidretrograde well.
 28. The pixel sensor cell of claim 22, wherein saidphotosensor is a photodiode sensor.
 29. The pixel sensor cell of claim22, wherein said photosensor is a photoconductor sensor.
 30. The pixelsensor cell of claim 22, further comprising a transfer gate locatedbetween said photosensor and said floating diffusion region.
 31. Thepixel sensor cell of claim 30, wherein said photosensor is a photogatesensor.
 32. The pixel sensor cell of claim 22, wherein the firstconductivity type is p-type, and the second conductivity type is n-type.33. The pixel sensor cell of claim 32, wherein said retrograde well isdoped with boron.
 34. The pixel sensor cell of claim 22, wherein thefirst conductivity type is n-type, and the second conductivity type isp-type.
 35. The pixel sensor cell of claim 34, wherein said retrogradewell is doped with a dopant selected from the group consisting ofarsenic, antimony, and phosphorous.
 36. A CMOS imager comprising: asubstrate having at least one epitaxial layer of a first conductivitytype; at least one retrograde well of a first conductivity type in saidat least one epitaxial layer; an array of pixel sensor cells formed insaid at least one retrograde well, wherein each pixel sensor cell has aphotosensor; and a circuit electrically connected to receive and processoutput signals from said array.
 37. The CMOS imager of claim 36, whereinsaid at least one epitaxial layer is a thermally grown epitaxial layer.38. The CMOS imager of claim 36, wherein said at least one epitaxiallayer has a thickness of about 10,000 Angstroms to about 150,000Angstroms.
 39. The CMOS imager of claim 38, wherein said epitaxial layerhas a thickness of about 30,000 Angstroms to about 100,000 Angstroms.40. The CMOS imager of claim 39, wherein said epitaxial layer has athickness of about 60,000 Angstroms.
 41. The CMOS imager of claim 36,wherein said at least one retrograde well comprises one retrograde well.42. The CMOS imager of claim 41, wherein said at least one retrogradewell comprises a plurality of retrograde wells, wherein said array isformed in a first retrograde well of said plurality, and said circuit isformed in a second retrograde well of said plurality.
 43. The CMOSimager of claim 42, wherein said first retrograde well is doped to afirst dopant level, and said second retrograde well is doped to a seconddopant level.
 44. The CMOS imager of claim 36, wherein each pixel sensorfurther comprises a floating diffusion region of a second conductivitytype located in said at least one retrograde well.
 45. The CMOS imagerof claim 36, wherein the first conductivity type is p-type, and thesecond conductivity type is n-type.
 46. The CMOS imager of claim 45,wherein said at least one epitaxial layer is an epitaxial silicon layer.47. The CMOS imager of claim 45, wherein said at least one retrogradewe'll is doped with boron.
 48. The CMOS imager of claim 36, wherein thefirst conductivity type is n-type, and the second conductivity type isp-type.
 49. The CMOS imager of claim 48, wherein said at least oneretrograde well is doped with a dopant selected from the groupconsisting of arsenic, antimony, and phosphorous.
 50. The CMOS imager ofclaim 36, wherein each pixel sensor cell further comprises a transfergate located between said photosensor and said floating diffusionregion.
 51. The CMOS imager of claim 50, wherein said photosensor is aphotogate sensor.
 52. The CMOS imager of claim 36, wherein saidphotosensor is a photodiode sensor.
 53. The CMOS imager of claim 36,wherein said photosensor is a photoconductor sensor.
 54. A method offorming a photosensor for an imaging device, said method comprising thesteps of: forming an epitaxial layer of a first conductivity type over asubstrate; forming a well of a first conductivity type in an uppersurface of said epitaxial layer; and forming a photosensor at an uppersurface of said well.
 55. The method of claim 54, wherein said epitaxiallayer is thermally grown.
 56. The method of claim 55, wherein saidepitaxial layer is a p-type epitaxial layer thermally grown at about900-1200° C.
 57. The method of claim 55, wherein said epitaxial layer isthermally grown to a thickness of about 10,000 Angstroms to about150,000 Angstroms.
 58. The method of claim 57, wherein said epitaxiallayer is grown to a thickness of about 30,000 Angstroms to about 100,000Angstroms.
 59. The method of claim 58, wherein said epitaxial layer isgrown to a thickness of about 60,000 Angstroms.
 60. The method of claim55, wherein said first conductivity type is p-type.
 61. The method ofclaim 55, wherein said first conductivity type is n-type.
 62. The methodof claim 55, wherein said well is formed by ion implantation.
 63. Amethod of forming a pixel cell for an imaging device, said methodcomprising the steps of: forming an epitaxial layer of a firstconductivity type over a substrate; forming a retrograde well of a firstconductivity type in said epitaxial layer; forming a photosensitiveregion in said retrograde well; forming a photosensor on an uppersurface of said photosensitive region for controlling the collection ofcharge therein; and forming a floating diffusion region of a secondconductivity type in said retrograde well for receiving chargestransferred from said photosensitive region.
 64. The method of claim 63,wherein said epitaxial layer is thermally grown.
 65. The method of claim64, wherein said epitaxial layer is a p-type epitaxial layer thermallygrown at about 900-1200° C.
 66. The method of claim 64, wherein saidepitaxial layer is thermally grown to a thickness of about 10,000Angstroms to about 150,000 Angstroms.
 67. The method of claim 66,wherein said epitaxial layer is grown to a thickness of about 30,000Angstroms to about 100,000 Angstroms.
 68. The method of claim 67,wherein said epitaxial layer is grown to a thickness of about 60,000Angstroms.
 69. The method of claim 63, wherein said first conductivitytype is p-type.
 70. The method of claim 63, wherein said firstconductivity type is n-type.
 71. The method of claim 63, wherein saidwell is formed by ion implantation.
 72. The method of claim 63 furthercomprising the step of forming a transfer gate on said retrograde well,between said photosensor and said floating diffusion region.
 73. Themethod of claim 72, wherein said photosensor is a photogate sensor. 74.The method of claim 63 further comprising the step of forming a resettransistor in said retrograde well for periodically resetting a chargelevel of said floating diffusion region, said floating diffusion regionbeing the source of said reset transistor.
 75. A method of forming apixel array for an imaging device, said method comprising the steps of:forming an epitaxial layer of a first conductivity type over asubstrate; forming a well of a first conductivity type in said epitaxiallayer; and forming a plurality of pixel sensor cells in said well,wherein each pixel sensor cell has a photosensitive region, aphotosensor formed on said photosensitive region for sensing charges ofa particular color wavelength, and a floating diffusion region of asecond conductivity type.
 76. The method of claim 75, wherein said firstconductivity type is n-type, and said second conductivity type isp-type.
 77. The method of claim 75, wherein said epitaxial layer isthermally grown.
 78. The method of claim 77, wherein said epitaxiallayer is a p-type epitaxial layer thermally grown at about 900-1200° C.79. The method of claim 75, wherein said epitaxial layer is thermallygrown to a thickness of about 10,000 Angstroms to about 150,000Angstroms.
 80. The method of claim 79, wherein said epitaxial layer isgrown to a thickness of about 30,000 Angstroms to about 100,000Angstroms.
 81. The method of claim 80, wherein said epitaxial layer isgrown to a thickness of about 60,000 Angstroms.
 82. The method of claim75, wherein said well is formed by ion implantation.
 83. A color pixelcell for an imaging device, said color pixel cell comprising: a first,second and third epitaxial layers of a first conductivity type formed ina substrate, said first, second and third epitaxial layers havingdifferent thicknesses in said substrate; a first, second and thirdphotosensitive regions formed in said respective first, second and thirdepitaxial layers for receiving first, second and third photochargescorresponding to a particular color wavelength; and a first, second andthird floating diffusion regions of a second conductivity type formed insaid respective first, second and third epitaxial layers for receivingsaid respective photocharges transferred from said respective first,second and third photosensitive regions.
 84. The color pixel cell ofclaim 83, wherein said first epitaxial layer, said first photosensitiveregion and said first floating diffusion region correspond to a redsensor cell of said imaging device.
 85. The color pixel cell of claim83, wherein said second epitaxial layer, said second photosensitiveregion and said second floating diffusion region correspond to a bluesensor cell of said imaging device.
 86. The color pixel cell of claim83, wherein said third epitaxial layer, said third photosensitive regionand said third floating diffusion region correspond to a green sensorcell of said imaging device.
 87. The color pixel cell of claim 83,wherein said first conductivity type is p-type, and said secondconductivity type is n-type.
 88. The color pixel cell of claim 87,wherein said first epitaxial layer is a p-type epitaxial silicon layerand is for a red sensor cell.
 89. The color pixel cell of claim 88,wherein said second epitaxial layer is a p-type epitaxial silicon layerand is for a blue sensor cell.
 90. The color pixel cell of claim 89,wherein said third epitaxial layer is a p-type epitaxial silicon layerand is for a green sensor cell.
 91. The color pixel cell of claim 83,wherein said first conductivity type is n-type, and said secondconductivity type is p-type.
 92. The color pixel cell of claim 83,wherein each of said respective first, second and third photosensitiveregions further comprises a respective photosensor for controlling thecollection of charges in said photosensitive region.
 93. The color pixelcell of claim 92, wherein each of said photosensor is a photodiodesensor.
 94. The color pixel cell of claim 92, wherein each of saidphotosensor is a photogate sensor.
 95. A method of forming a color pixelcell for an imaging device, said method comprising the steps of: formingat least three epitaxial layers of a first conductivity type in asubstrate, said at least three epitaxial layers having differentthicknesses in said substrate; forming a photosensitive region in eachof said at least three epitaxial layers; forming a photosensor on anupper surface of said photosensitive region for receiving charges of aparticular color wavelength; and forming a floating diffusion region ofa second conductivity type in each one of said at least three epitaxiallayers for receiving charges transferred from said photosensitiveregion.
 96. The method of claim 95, wherein said first conductivity typeis p-type, and said second conductivity type is n-type.
 97. The methodof claim 95, wherein said first conductivity type is n-type, and saidsecond conductivity type is p-type.
 98. The method of claim 95 furthercomprising the step of forming a transfer gate on each of said at leastthree epitaxial layers, between said photosensor and said floatingdiffusion region.
 99. The method of claim 95 further comprising the stepof forming a reset transistor in each of said at least three epitaxiallayers for periodically resetting a charge level of said floatingdiffusion region, said floating diffusion region being the source ofsaid reset transistor.
 100. A color pixel cell for an imaging device,said color pixel cell comprising: at least three epitaxial layers of afirst conductivity type formed in a substrate, said at least threeepitaxial layers having different thicknesses in said substrate; atleast three photosensitive regions formed in said respective at leastthree epitaxial layers for receiving at least three photochargescorresponding to a particular color wavelength; and at least threefloating diffusion regions of a second conductivity type formed in saidrespective at least three epitaxial layers for receiving said respectivephtocharges transferred from said respective at least threephotosensitive regions.
 101. The color pixel cell of claim 100, whereineach of said at least three epitaxial layers, of said at least threephotosensitive regions and of said at least three floating diffusionregions correspond to a particular color sensor cell of said imagingdevice.
 102. The color pixel cell of claim 100, wherein said firstconductivity type is p-type, and said second conductivity type isn-type.
 103. The color pixel cell of claim 100, wherein one of said atleast three epitaxial layers is a p-type epitaxial silicon layer and isfor a red sensor cell.
 104. The color pixel cell of claim 100, whereinone of said at least three epitaxial layers is a p-type epitaxialsilicon layer and is for a blue sensor cell.
 105. The color pixel cellof claim 100, wherein one of said at least three epitaxial layers is ap-type epitaxial silicon layer and is for a green sensor cell.
 106. Thecolor pixel cell of claim 100, wherein said first conductivity type isn-type, and said second conductivity type is p-type.
 107. The colorpixel cell of claim 100, wherein each of said respective at least threephotosensitive regions further comprises a respective photosensor forcontrolling the collection of charges in said photosensitive region.108. The color pixel cell of claim 107, wherein each of said photosensoris a photodiode sensor.
 109. The color pixel cell of claim 107, whereineach of said photosensor is a photogate sensor.